1. The Field of the Invention
The present invention relates to processes for constructing conductive interconnects. More specifically, the present invention relates to processes for constructing a plurality of conductive interconnects on sub-micron semiconductor devices.
2. The Relevant Technology
Integrated circuits are manufactured by an elaborate process in which a variety of different microelectronic devices are integrally formed on a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) structure. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices can be formed on a single substrate.
One of the steps in the fabrication of integrated circuits is to form generally horizontal conducting, e.g., metallic, interconnection or wire lines between the discrete microelectronic devices on the integrated circuit and to external circuitry. The horizontal interconnections are conducting layers that permit an electrical current to be delivered to and from the various microelectronic devices so that the integrated circuit can perform its intended function. Since the integrated circuitry needed for a semiconductor is usually build-up three-dimensionally on the substrate in order to increase the packing density and so forth, multilevel metallizations or conductors are generally necessary and employed. It will be appreciated that this necessitates the provision of inter-level dielectric layers interposed between different conductor levels formed on the device substrate.
Vias, also referred to as xe2x80x9cvertical interconnectsxe2x80x9d or simply xe2x80x9cinterconnects,xe2x80x9d are used to electrically connect different horizontal levels of metallization or conductors. The interconnect is a via hole or through hole filled with a conductor material that extends through a dielectric interposed between surfaces of two separate horizontal conductor levels. It will be appreciated that the layering process is repeated as needed to form additional levels and to form a plurality of similar horizontal and vertical conductive interconnections. Among other things, the yield, performance and reliability of the semiconductor device depend to a large extent on the accuracy of placement of the through hole with respect to the active regions of the individual semiconductor devices.
U.S. Pat. No. 5,869,403, which patent is incorporated herein by reference for all purposes, discloses formation of contact openings over a substrate in which an interconnect, e.g., a conducting polysilicon plug can be formed. Since many layers of material overlie the substrate, forming a desired contact opening necessarily involves etching through different overlying layers of material.
Referring to FIGS. 1-3, a semiconductor wafer fragment is shown generally at 10. Fragment 10 includes a top surface 12 atop which two laterally spaced apart conductive lines 14 are formed. Lines 14 comprise respective polysilicon layers 16, silicide layers 18, and insulative nitride caps 20, all of which having been formed by a previous anisotropic etch. Lines 14 also include insulative sidewall spacers 22. It will also be appreciated that the lines 14 can be fabricated over a thin oxide layer 23. However, since such details are well known to one of ordinary skill in the art, and since the presence or absence of such well known structure has no impact on either the art discussed in this section or the invention discussed below, fine details are omitted unless critical to understanding the present invention. It should also be noted that conductive lines 14 may form gates of transistor structures and that doped regions may be present in the silicon substrate 15 on either side of conductive line 14. A thin oxide layer 24 is typically formed over the substrate and conductive lines 14, and typically is composed of an oxide formed from decomposition of tetraethyloxysilane (TEOS). A layer 26 of borophosphosilicate glass (BPSG) is typically formed over layer 24 as shown.
FIG. 2 illustrate one possible problem associated with forming a contact opening to wafer or substrate 10, wherein a contact opening 28 is anisotropically etched between conductive lines 14 to a degree sufficient to expose an area 30 of the substrate between the conductive lines and to which electrical connection is to be made. As the conductive lines 14 are pushed closer together, etching to surface 30 may also produce destructive etching of one or more layers associated with conductive lines 14. It will be appreciated that this problem occurs more often as the device density increases. Typical etch chemistries for etching contact opening 28 etch BPSG layer 26 at a much faster rate than TEOS layer 24. Accordingly, when the anisotropic etch reaches TEOS layer 24 between contact lines 14 (FIG. 1), the etch must be conducted for a longer period of time to thereby ensure that TEOS layer 24 is completely removed to adequately expose area 30. This etch, due in part to the differing etch rates between TEOS layer 24 and BPSG layer 26, can overetch the inner-most side wall spacers 22 and erode nitride cap 20 thereby undesirably exposing silicide 18 as shown for the right-most conductive line 14 in FIG. 2. The resulting condition can, and does, cause shorting between adjacent lines or devices when a polysilicon plug is formed in the etched area, thereby rendering the device useless.
FIG. 3 illustrates one proposed solution to the above-described problem, wherein contact opening 28 is made to be narrower between conductive lines 14. As shown, the sides of contact opening 28 coincide with inner-most side wall spacers 22 so that the risk of overetching the side wall spacers and hence nitride caps 20 and silicide 18 is reduced. However, limiting the contact opening width, with the reduced risk of overetching, places severe constraints on the photomask and the alignment processes used to define contact opening 28. It also produces a high aspect ratio (height to width of the etched area) which is harder to later fill with a conductor.
Another semiconductor wafer fragment is indicated generally by reference numeral 32 in FIG. 4, which is provided to illustrate an alternative method of producing interconnect vias. The fragment 32 includes a substrate 34 having a top surface 36. A pair of conductive lines 38 are formed atop surface 36 and over substrate 34 by patterning and etching respective layers of polysilicon 40, silicide 42 and nitride 44. Nitride layers 44 form protective caps over the conductive lines. Sidewall spacers 46, preferably also formed from nitride, are formed over conductive lines 38 and together with nitride caps 44 form a protective encapsulating layer. Conductive lines 38 constitute a pair of nitride insulated conductive lines between which electrical connection to substrate 34 is to be made. It will be noted that lines 38 are formed adjacent a substrate contact area 48 with which the electrical connection will be made.
A first oxide layer 50 is formed over substrate 34 and between conductive lines 38 covering at least part and preferably all of contact area 48. In the illustrated and preferred example, layer 50 is an undoped oxide layer which is formed or deposited by decomposition of TEOS to a thickness of from about 300-500 Angstroms. A second oxide layer 52 is formed over first oxide layer 50 and is preferably formed from a different oxide material than layer 50. It should be noted that second oxide layer 52 comprises a doped oxide layer of BPSG, which is formed or deposited over first layer 50 to a thickness of about 10,000-14,000 Angstroms. Thus, first oxide layer 50 is interposed between the substrate and second oxide layer 52, i.e., directly beneath the second oxide layer.
FIG. 4 broadly illustrates the resultant semiconductor wafer fragment following a semiconductor processing method wherein a first oxide layer 50 is formed over the substrate to cover at least part of the contact area and a second oxide layer 52 is formed over the first oxide layer, the first and second oxide layers being different from one another. A first etch is then conducted over the contact area and through the second oxide layer to a degree sufficient to leave at least a portion of the first oxide layer over the contact area, i.e., the area denotes as w2, in FIG. 4. A second etch is then conducted to a degree sufficient to remove substantially all of the first oxide layer left behind and to remove a desired amount of the second oxide layer laterally outwardly of the contact area, i.e., the area denoted as w2 in FIG. 4. As mentioned above, the first oxide layer can be TEOS while the second oxide layer can be BPSG. BPSG in the vicinity of the contact opening is removed by a conventional anisotropic etch. TEOS and residual BPSG is removed by an isotropic etch using an aqueous solution comprising fluorine and having less than or equal to about 10% by weight of an etch rate changing surfactant which etches the second oxide layer at a slower rate than the first oxide layer. In short, the second etch minimizes the overetching problems illustrated in FIG. 2.
The processing method of controllably widening a contact opening by exposing the opening to an aqueous solution comprising fluorine, and having an added surfactant, after first anisotropically etching the contact opening, described in connection with FIG. 4, has several advantages over the processes described with respect to FIG. 2 or FIG. 3. First, the initial anisotropic dry etch does not have to be conducted for as long a period of time in an attempt to clear all of the oxide from the bottom of the contact area 48, which results in reducing or virtually eliminating the risk of over etching inner-most side wall spacers 46 and causing undesirable shorts as mentioned above. Any remaining oxide will be etched by the subsequently conducted wet etch which selectively etches the preferred TEOS and BPSG layers 50, 52 respectively, relative to nitride side wall spacers 46 and nitride caps 44, as illustrated in FIG. 4. Additionally, the above-described method reduces the risk of damaging the substrate surface adjacent contact area 48 because such area will be cleared by the subsequently conducted wet etch. Such wet etch is much less destructive to the silicon surface than the previously conducted anisotropic dry etch.
From the discussion of FIGS. 1-4 above, it will be appreciated that the proposed solutions to the overetching problems require initial formation of through holes which are smaller that the polysilicon plug that is to be formed over the contact opening. In many cases, the initial width of the through holes may be less than that of either of the conductive lines 38. It will be appreciated that this increases the precision needed for mask design and alignment during the various processing steps. It will also be appreciated that the requisite precision increases geometrically as semiconductor technology migrates from 0.25 micron to 0.18 micron to 0.13 micron processes.
What is needed is a process for forming a plurality of interconnects wherein each step of the process permits one dimensional control of the masking or printing process. Moreover, what is needed is a process for forming interconnects wherein each mask includes features which are greater than or equal to one line width. It would be highly desirable if the process for forming multiple interconnects could employ masks based on masks employed in fabricating conducting lines, e.g., wordlines, and active regions of the semiconductor device.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the pertinent art which mitigates the above-described deficiencies.
In one aspect, the present invention provides a process for forming N polysilicon interconnects in a semiconductor device, where N is a positive integer greater than or equal to two. Preferably, the process includes steps for depositing a monolithic polysilicon plug covering N contact openings, and etching Nxe2x88x921 through holes in the polysilicon plug to thereby separate the polysilicon plug into N polysilicon interconnects.
In another aspect, the present invention provides a process for forming a plurality of polysilicon interconnects associated with a respective plurality of contact openings in a semiconductor device, comprising steps of providing a workpiece having an active area and a plurality of potential contact openings covered with a dielectric layer, etching a first through hole in the dielectric layer to expose the plurality of contact openings, depositing a polysilicon plug in the first through hole, and etching at least one second through hole in the polysilicon plug to thereby divide the polysilicon plug into the polysilicon interconnects.
In another aspect, the present invention provides a semiconductor processing method for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device. The semiconductor processing method advantageously includes steps for providing a workpiece having an active area and N potential contact openings covered with a dielectric layer, etching a first through hole in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching Nxe2x88x921 second through holes in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2. According to one aspect of the inventive processing method, the workpiece includes Nxe2x88x921 conductors traversing the active area, the N contact openings are disposed adjacent to the Nxe2x88x921 conductors, and each of the N contact openings is separated from the other contact openings by one of the Nxe2x88x921 conductors. In an exemplary case, the conductors are wordlines in a memory device.
In another aspect, the present invention provides a semiconductor processing method for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device, including steps for providing a workpiece having an active area and N potential contact openings covered with first and second dielectric layers, etching a first hole in the first dielectric layer over substantially all of the workpiece corresponding to the active area using a first etch process, etching a first through hole in the first and second dielectric layers to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings using a second etch process, depositing a monolithic polysilicon plug in the first through hole, and etching, using a third etch process, Nxe2x88x921 second through holes in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2.
In another aspect, the present invention provides a semiconductor processing method for forming Mxc3x97N polysilicon interconnects coupled to Mxc3x97N contact openings in a semiconductor array including at least M discrete devices. Preferably, the processing method includes steps of providing a workpiece having M active areas, each active area having N potential contact openings covered with first and second dielectric layers, etching M first holes in the first dielectric layer over substantially all of the workpiece corresponding to the M active areas using a first etch process, etching M first through holes in the first and second dielectric layers to expose substantially all of the workpiece corresponding to the M active areas to thereby expose the Mxc3x97N contact openings using a second etch process, depositing a monolithic polysilicon plug in the M first through holes to thereby form M polysilicon plugs, and etching, using a third etch process, Mxc3x97(Nxe2x88x921) second through holes in the M polysilicon plugs to thereby divide the M polysilicon plugs into the Mxc3x97N polysilicon interconnects. In an exemplary case, N is an integer greater than or equal to 2 and M is an integer orders of magnitude greater than N.
In another aspect, the present invention provides a semiconductor processing method for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device, comprising steps for providing a workpiece having an active area and N potential contact openings covered with a dielectric layer, etching a first through hole having first and second dimensions in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching Nxe2x88x921 second through holes, each having third and fourth dimensions in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects. In one exemplary embodiment of the present invention, N is an integer greater than or equal to 2, the first dimension is greater than the second dimension, the second dimension of the first through hole is aligned with the short axis of the active area, the third dimension is greater than the fourth dimension, and the fourth dimension of each of the Nxe2x88x921 second through holes is aligned with a predetermined portion of the active area perpendicular to the long axis of the active area.
In another aspect, the present invention provides a semiconductor processing method for forming N polysilicon interconnects coupled to N contact openings in a semiconductor device, which method includes steps for providing a workpiece having an active area and N potential contact openings covered with first and second dielectric layers, etching a first hole having first and second dimensions in the first dielectric layer over substantially all of the workpiece corresponding to the active area using a first etch process, etching a first through hole have the first and the second dimensions in the second dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings using a second etch process, depositing a monolithic polysilicon plug in the first through hole, and etching, using a third etch process, Nxe2x88x921 second through holes, each having third and fourth dimensions, in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects. In one exemplary embodiment, N is an integer greater than or equal to 2, the first dimension is greater than the second dimension, the second dimension of the first through hole is aligned with the short axis of the active area, the third dimension is greater than the fourth dimension, and the fourth dimension of each of the Nxe2x88x921 second through holes is aligned with a predetermined portion of the active area perpendicular to the long axis of the active area.
In another aspect, the present invention provides a semiconductor processing method for forming a pair of memory cells connected to a common digitline, wherein an active area corresponding to the memory cells includes 3 contact openings permitting connection of first and second storage capacitors and the common digitline via 3 polysilicon interconnects coupled to 3 contact openings in a semiconductor device. In one exemplary embodiment, the method includes steps for providing a workpiece having an active area and 3 potential contact openings covered with a dielectric layer, etching a first through hole in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the 3 contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching 2 second through holes in the polysilicon plug and disposed between the 3 contact openings to thereby divide the polysilicon plug into the 3 polysilicon interconnects.
In another aspect, the present invention provides a semiconductor processing method for forming a pair of memory cells connected to a common digitline, wherein an active area corresponding to the memory cells includes 3 contact openings permitting connection of first and second storage capacitors and the common digitline via 3 polysilicon interconnects coupled to 3 contact openings, wherein the inventive method includes steps for providing a workpiece having an active area and 3 potential contact openings covered with first and second dielectric layers, etching a first hole in the first dielectric layer over substantially all of the workpiece corresponding to the active area using a first etch process, etching a first through hole in the first and second dielectric layers to expose substantially all of the workpiece corresponding to the active area to thereby expose the 3 contact openings using a second etch process, depositing a monolithic polysilicon plug in the first through hole, and etching, using a third etch process, 2 second through holes in the polysilicon plug and disposed between the 3 contact openings to thereby divide the polysilicon plug into the 3 polysilicon interconnects.
In another aspect, the present invention provides a semiconductor processing method for forming a memory cell array of M elements, each element of the array including a pair of memory cells connected to a common digitline, wherein an active area corresponding to each pair of memory cells includes 3 contact openings permitting connection of first and second storage capacitors and the common digitline via 3 polysilicon interconnects coupled to 3 contact openings to thereby forming 3M polysilicon interconnects coupled to 3M contact openings. Preferably, the semiconductor proceeding method includes steps for providing a workpiece having M active areas, each active area having 3 potential contact openings covered with first and second dielectric layers, etching M first holes in the first dielectric layer over substantially all of the workpiece corresponding to the M active areas using a first etch process, etching M first through holes in the first and second dielectric layers to expose substantially all of the workpiece corresponding to the M active areas to thereby expose the 3M contact openings using a second etch process, depositing a monolithic polysilicon plug in the M first through holes to thereby form M polysilicon plugs, and etching, using a third etch process, 2M second through holes in the M polysilicon plugs to thereby divide the M polysilicon plugs into the 3M polysilicon interconnects. In an exemplary case, M is an integer greater than 1000, although M advantageously can be several orders of magnitude larger than 1000.
In another aspect, the present invention provides a memory device including a memory chip comprising a memory circuit fabricated on the memory chip. Preferably, the memory circuit includes an active area, N elements disposed above the active and separated from the active area by at least one dielectric layer, and N vertical polysilicon interconnects electrically connecting N contact openings associated with the active area with the N elements. Most preferably, the polysilicon interconnects are formed by the process of providing a workpiece having the active area and N potential contact openings covered with the dielectric layer, etching a first through hole in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching Nxe2x88x921 second through holes in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2.
In another aspect, the present invention provides a memory module, comprising a die substrate comprising a circuit board, a plurality of memory chips mounted on the circuit board, wherein one or more of the memory chips comprise a memory circuit fabricated on the semiconductor chip for communicating with a processor, where the memory circuit advantageously includes an active area, N elements disposed above the active and separated from the active area by at least one dielectric layer, and N vertical polysilicon interconnects electrically connecting N contact openings associated with the active area with the N elements. According to one aspect of the invention, the N polysilicon interconnects are formed by the process of providing a workpiece having the active area and N potential contact openings covered with the dielectric layer, etching a first through hole in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching Nxe2x88x921 second through holes in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2.
In another aspect, the present invention provides a processor system, which includes a processor, and memory circuit fabricated on a semiconductor chip communicating with the processor. Preferably, the memory circuit includes an active area, N elements disposed above the active area and separated from the active area by at least one dielectric layer, and N vertical polysilicon interconnects electrically connecting N contact openings associated with the active area with the N elements. Most preferably, the N polysilicon interconnects are formed by the process of providing a workpiece having the active area and N potential contact openings covered with the dielectric layer, etching a first through hole in the dielectric layer to expose substantially all of the workpiece corresponding to the active area to thereby expose the N contact openings, depositing a monolithic polysilicon plug in the first through hole, and etching Nxe2x88x921 second through holes in the polysilicon plug and disposed between the N contact openings to thereby divide the polysilicon plug into the N polysilicon interconnects, where N is an integer greater than or equal to 2.
The invention simplifies the alignment process of fabricating a conductor down to a desired surface of an integrated circuit device.